The present invention relates in general to circuits employed for the generation of reference currents and/or reference voltages, and is particularly directed to a new and improved multi transistor-configured reference current and voltage generator, that is effectively insensitive to variations in power supply voltage and temperature.
FIGS. 1, 2 and 3 respectively depict conventional bipolar, CMOS and BiCMOS current mirror transistor circuits, that are widely used throughout the electronics industry to generate a reference current IOUT, that is to be supplied to one or more signal processing circuits of an integrated circuit architecture. xe2x80x98Ideallyxe2x80x99, this reference current IOUT may be defined by equation (1) as:                               I          OUT                =                                            KT              q                        *                                          ln                ⁡                                  (                  N                  )                                            R1                                =                                    V              T                        *                                          ln                ⁡                                  (                  N                  )                                            R1                                                          (        1        )            
Using the bipolar transistor configuration of FIG. 1 as a representative example of the set of three current generator circuits, the ideal value for its output reference current IOUT is based upon the assumption that the current mirror transistors in the two legs of the generator are perfectly matched and that each of the bipolar transistors Q1/Q2, Q4/Q5 has infinite hfe or beta. Namely, if current mirror transistor pair Q1 and Q2 are perfectly matched, the collector current through transistor Q1 in one leg of the circuit is equal to the collector current flowing through transistor Q2 in the opposing leg. Also, if the current mirror transistor pair Q4 and Q5 have infinite hfe or beta, the emitter current of transistor Q4 will be the same as the emitter current of Q5, which equals the current through resistor R1. The relationship between these currents is summarized in equation (2) as follows:
IC(Q1)=IC(Q2)=IC(Q4)=IC(Q5)=IE(Q4)=IE(Q5)=IRI=IOUTxe2x80x83xe2x80x83(2)
In addition, the voltage drop VBE(Q4) across the base-emitter junction of transistor Q4 will equal the voltage drop VBE(Q5), plus the voltage drop across resistor R1, as set forth in equation (3) as follows:
VBE(Q4)=VBE(Q5)+IOUT*R1xe2x80x83xe2x80x83(3).
It is well known that the VBE of a bipolar transistor is equal to the natural log (ln) of the ratio of its collector-emitter current (I) to the saturation current (Is), as set forth in equation (4).                               V          BE                =                                            KT              q                        *                          ln              ⁡                              (                                  I                                      I                    s                                                  )                                              =                                                    KT                q                            *                              ln                ⁡                                  (                                      I                                                                  EmitterArea                        ⁡                                                  (                          Q5                          )                                                                    *                                              Js                        ⁡                                                  (                          Q5                          )                                                                                                      )                                                      =                                          V                T                            *                              ln                ⁡                                  (                                      I                                                                  EmitterArea                        ⁡                                                  (                          Q5                          )                                                                    *                                              Js                        ⁡                                                  (                          Q5                          )                                                                                                      )                                                                                        (        4        )            
The saturation current (Is) can be rewritten as the emitter area of the transistor multiplied by the saturation current per unit area, or the saturation current density (Js), as also shown in equation (4). Substituting this expression for VBE into equation (3) yields equation (5), as follows:                                           V            T                    *                      ln            ⁡                          (                              I                                                      EmitterArea                    ⁡                                          (                      Q4                      )                                                        *                                      Js                    ⁡                                          (                      Q4                      )                                                                                  )                                      =                                            V              T                        *                          ln              ⁡                              (                                  I                                                            EmitterArea                      ⁡                                              (                        Q5                        )                                                              ⁢                                          Js                      ⁡                                              (                        Q5                        )                                                                                            )                                              +                      I            *            R1                                              (        5        )            
The saturation current densities for transistors with the same doping profiles, formed in the same substrate, and using the same processing steps, will match each other extremely well. As a consequence, it may be inferred that the saturation current density of the transistor Q4 of the current generator of FIG. 1 equals the saturation current density of transistor Q5, as defined in equation (6).
Js(Q4)=Js(Q5)=Js(npn)xe2x80x83xe2x80x83(6)
Equation (7), set forth below, shows that current mirror transistors Q4 and Q5 of the current generator of FIG. 1 are designed such that the ratio of the emitter area of transistor Q5 to the emitter area of transistor Q4 is set to a known constant N, defined in equation (7) as:
N=EmitterArea(Q5)/EmitterArea(Q4)xe2x80x83xe2x80x83(7)
Solving equation (5) for I and substituting into equations (6) and (7) yields equation (8), as follows:
                    I        =                                            V              T                        *            ln            ⁢                          xe2x80x83                        ⁢                                          (                                                      I                    *                                          EmitterArea                      ⁡                                              (                        Q5                        )                                                              *                                          Js                      ⁡                                              (                        Q5                        )                                                                                                  I                    *                                          EmitterArea                      ⁡                                              (                        Q4                        )                                                              *                                          Js                      ⁡                                              (                        Q4                        )                                                                                            )                            R1                                =                                                    V                T                            *                              ln                ⁡                                  (                  N                  )                                                      R1                                              (        8        )            
The sensitivity of a circuit to changes in its power supply voltage is called power supply rejection (PSR). If a circuit had infinite PSR, the output of that circuit would not be affected by changes in the power supply voltage. Although equation (8) implies that the reference current IOUT generated by the current mirror transistor circuits of the current generator architecture of FIGS. 1 through 3 is independent of its power supply voltage Vcc, this equation assumes infinite hfe and xe2x80x98perfectly matchedxe2x80x99 current mirror transistors. In a practical circuit, however, the early voltage effect, shown in the collector current vs. collector-emitter voltage characteristic of FIG. 4, will cause mismatches in the current mirrors.
In the bipolar configuration of FIG. 1, for example, the early voltages of the two current mirror transistors Q1 and Q2 will cause a mismatch in their collector currents, since the collector-emitter voltage VCE of transistor Q1 is not equal to the collector-emitter voltage VCE of transistor Q2. This difference in collector-emitter voltages is due to the fact that the collector-emitter voltage (VCE) of transistor Q1 equals the power supply voltage rail differential (Vccxe2x88x92GND) minus the base-emitter voltage (VBE) to GND rail differential (e.g., approximately 0.7V) of diode-connected transistor Q4.
For a Vcc=5V power supply, therefore, the VCE of transistor Q1 would be approximately equal to (5.0-0.7=) 4.3 volts. Since, however, its associated current mirror transistor Q2 is diode-connected, the VCE of transistor Q2 equals its VBE (0.7V), or about one-sixth of that of transistor Q1. This mismatch in the VCE voltages of the current mirror transistors Q1 and Q2 results in a mismatch in their collector currents (even though the VBE voltages of Q1 and Q2 are identical).
Such mismatches in the current mirrors will cause the reference current IOUT to deviate from the ideal value set forth in Equation (8). This problem is made worse by the fact that the mismatch in the current mirror transistors will change as the power supply voltage varies. Therefore, due to the early voltage effect alone, the reference current IOUT generated by the circuits shown in FIGS. 1 through 3 is not independent of power supply voltage variation.
This can be a significant problem in low voltage applications having reduced power supply xe2x80x98headroomxe2x80x99, where high power supply rejection is required. Such headroom limitations are becoming increasingly common as the industry continues to use lower and lower power supply voltages. To solve this problem in a bipolar circuit of the type shown in FIG. 1, it has been proposed to couple an auxiliary bias amplifier in circuit with one of the legs of the current generator, as diagrammatically illustrated in FIG. 5, and as described, for example, in an article by M. Gunawan et al, entitled: xe2x80x9cA Curvature-Corrected Low Voltage Bandgap Referencexe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 28, No. 6, June 1993, pp 667-670, and also in an article by H. Nauta et al, entitled: xe2x80x9cNew Class of High-Performance PTAT Current Sources,xe2x80x9d Electronics Letters, Apr. 25, 1985, Vol. No. 9, pp 384-386.
In the bipolar scheme of FIG. 5, the voltages across associated transistors of the two current mirror legs of the current generator are effectively equalized by means of an auxiliary bias amplifier 50, formed of a current mirror PNP transistor Q51 and a VCE-controlling NPN transistor Q55. These two bias amplifier transistors have their collector-emitter current paths connected in parallel with those of transistor pairs Q52/Q53 and Q56/Q57, of the two current mirror legs that are connected between the power supply rails (Vcc and ground).
The first polarity (PNP) transistor Q51 of the auxiliary bias amplifier 50 is connected in a diode configuration (having its collector connected to its base), with the base electrode of PNP transistor Q51 being connected in common to the bases of PNP transistors Q52 and Q53, and Q54 with which auxiliary transistor Q51 forms a current mirror. The base of the second polarity (NPN) transistor Q55 of the auxiliary bias amplifier is coupled to the collector current path of that leg of the current generator containing PNP current mirror transistor Q52 and NPN current mirror transistor Q56. The PNP transistor Q51 of the bias amplifier 50 is matched with PNP current mirror transistors Q52 and Q53, and Q54, and NPN transistor Q55 is matched with NPN current mirror transistor Q56 and scaled with NPN transistor Q57.
The bias amplifier transistors Q51 and Q55 operate at the same current level as the current mirror transistors of the two legs of the current generator, and the bias amplifier 50 biases the PNP current mirror transistor pair Q52 and Q53 to produce currents that are equal to the current in the bias amplifier""s PNP transistor Q51, by means of current mirror action with PNP transistor Q52.
Adding the bias amplifier circuit results in a positive feedback circuit containing transistors Q55-Q51 for the base drive to the current mirror transistors Q52 and Q53, and serving to clamp the collector voltages of current mirror transistors Q56 and Q57 at the same base-emitter voltage (VBE55=VBE56) of transistors Q55 and Q56, respectively. In addition, a negative feedback circuit is formed by transistor Q57 and resistor R51. For stability, the gain of the negative feedback circuit may be made greater than that of the positive feedback circuit, by connecting a capacitor across the base and collector of transistor Q55, so as to provide a rapid roll-off in the gain of the positive feedback circuit at high frequencies.
In operation, with the base of the VCE-controlling NPN transistor Q55 connected to the collector of NPN transistor Q56, any current differences between transistors Q55 and Q56 are due to base currents required by the PNP transistors Q51 through Q54, and differences in the collector-emitter voltages VCE of the two NPN transistors Q55 and Q56. If the first set of matched PNP transistors Q51-Q54 have reasonably high betas, their base currents will cause only a small percentage of error. Also, the early voltage effects described above with reference to FIG. 4 will cause only small differences in their collector currents.
The NPN transistor Q55 clamps the collector voltage of NPN transistor Q56 in the leg containing transistor Q52 at one base-emitter voltage (VBE55) above the supply rail (GND) to which its emitter is connected. With transistors Q55 and Q56 being matched, and with the base of the NPN transistor Q56 connected to the collector of the NPN transistor Q57 in the leg containing transistor Q53, then the NPN transistor Q56 similarly clamps the collector voltage of NPN transistor Q57 at one base-emitter voltage (VBE56) above the supply rail (GND) to which its emitter is connected. Therefore, the VCE of the current mirror transistor Q56 will be very close to that of current mirror transistor Q53. As a result, the current through the leg containing PNP transistor Q52 and NPN transistor Q56 will effectively match the current through the leg containing PNP transistor Q53 (which is mirrored with transistor Q52) and NPN transistor Q57 (which is ratioed with transistor Q56). This means that the current IOUT generated at the collector of the output transistor Q54 will be effectively insensitive to variations in the power supply rail voltages.
In accordance with the present invention, the ability of the auxiliary bias amplifier-incorporating current generator circuit architecture of FIG. 5 to reduce its sensitivity to variations in power supply voltage is augmented by means of temperature compensation circuitry that is effective to make the current generator insensitive to variations in temperature. As will be described, temperature insensitivity is achieved by generating a current that is the sum or composite of two currents having complementary temperature coefficients.
One current has a positive temperature coefficient, being proportional to KT/q (where K is Boltzman""s constant, T is temperature xc2x0K. and q is charge), divided by the value of a first resistor connected between the emitter of a second polarity current mirror transistor and a power supply rail. The second current (which has a negative temperature coefficient) flows through a second resistor and is proportional to the VBE of a second polarity current mirror transistor divided by the resistance of a second resistor, connected across the base-emitter junction of the second polarity current mirror transistor.
Since this second current has a negative temperature coefficient, the sum of the two currents at the collector of a current mirror transistor can be set to have a positive, negative, or near zero temperature coefficient, based upon the ratioing of the two currents. The generated output current can be made relatively insensitive to both supply voltage variations and temperature changes, as long as a proper resistor ratio is employed.
To minimize any effect of temperature change, the resistors are preferably made of a material having as low a temperature coefficient as possible. The ability of the augmented generator circuit of the invention to provide an output current that is insensitive to variations in power supply voltage and temperature means that the output current may also be used to generate a stable reference voltage, such as that provided by a bandgap voltage generator.
In accordance with a further aspect of the invention, there is provided a new and improved CMOS current generator architecture, which incorporates an auxiliary CMOS amplifier that is configured and biased to reduce its sensitivity to variations in power supply voltage. Like a augmented bipolar current generator, the CMOS current generator may be augmented by temperature compensation circuitry, so as to provide an output current that is insensitive to both variations in power supply voltage and temperature. As such, the CMOS configured circuit of the invention may also be used to generate a stable reference voltage.